CMOS integrated circuits are widely used for logic, memory, microprocessor and other microelectronic devices. As is well known to those having skill in the art, CMOS integrated circuits include insulated gate field effect transistors of complementary conductivity types, often referred to as NMOS transistors and PMOS transistors, on a single integrated circuit. Although the acronym MOS actually stands for metal oxide silicon, it will be understood that this term as used herein refers to any insulated gate field effect transistor.
As the integration density of integrated circuit devices continues to increase, it may become more difficult to ensure that CMOS devices can be reliably manufactured. For example, as the integration density of an integrated circuit device increases, and the design rules for fabricating the integrated circuit device continue to decrease, the size of a contact hole may extend into submicron dimensions. With such small dimensions, it may become difficult to ensure adequate overlap margins and reliable fabrication methods. Accordingly, there continues to be a need for CMOS integrated circuits and fabrication methods which can reduce the likelihood of overlap between regions thereof, notwithstanding decreasing device dimensions.
FIG. 1 is a schematic plan view of a conventional CMOS integrated circuit. Referring to FIG. 1, reference numerals P1 and P2 denote mask patterns for forming N-type and P-type active regions respectively. P3 and P4 denote mask patterns for forming the gates of NMOS and PMOS transistors, respectively. P5 and P6 denote mask patterns for forming contact holes connecting the source/drains of the NMOS or PMOS transistors to a wiring layer, respectively. Reference 1 denotes the distance between semiconductor devices, x1 denotes the overlap margin between a gate and a contact hole, and x2 and y denote overlap margins of an active region with respect to a contact hole in the direction of the x and y axis, respectively.
The decrease in design rules due to high integration of integrated circuit devices may cause a decrease of the overlap margin between an active region and a contact hole. Moreover, the x1, x2, and y values may decrease to under 0.1 .mu.m for a DRAM of over 64 Mbits.
Techniques have been proposed in attempts to overcome these problems. For example, the contact hole size may be reduced to thereby improve overlap margin. The distance between integrated circuit devices may be decreased, allowing more space for contact holes. The overlap margin (x1) between a gate and a contact hole or the overlap margins (x2, y) of the active region may also be decreased.
Unfortunately, these techniques may require a misalignment of less than 0.1 .mu.m, which may make it difficult to adopt these techniques for high volume fabrication. Moreover, decreasing contact hole size may also increase the contact resistance, which may deteriorate device operating speed. The aspect ratio of a contact hole may also increase, which may make it difficult to fill the contact hole.
FIGS. 2A through 2D are cross-sectional views showing a conventional manufacturing method of a CMOS integrated circuit whose NMOS source/drain includes a lightly doped drain (LDD) structure. Referring to FIG. 2A, a field oxide 4 for separating active regions and inactive regions is formed on the surface of an integrated circuit substrate such as a semiconductor substrate 2, and then an N-well 6 and a P-well are formed using a conventional well forming process. A gate insulating layer 8 is then formed on the substrate 2, and impurity-doped polysilicon is deposited thereon and patterned to form a gate electrode 10.
Referring to FIG. 2B, a low concentration of N-type impurity ions are implanted into the semiconductor substrate 2 using the gate electrode 10 as a mask, in order to form an N.sup.- source/drain 12. This implant step generally is not limited to the NMOS transistor area in order to reduce the number of process steps. As a result, the P.sup.- source/drain 14 in the N-well 6 can suppress short channel effects of the PMOS transistor.
An insulating material then is deposited on the substrate 2 and is patterned in order to form an insulating layer 16. Then, a high concentration of impurity ions are implanted into the NMOS and PMOS transistor areas of the semiconductor substrate using the insulating layer 16 and photoresist patterns for NMOS and PMOS (not shown in the FIG. 2B) as a mask, in order to form a N.sup.+ source/drain 18 and P.sup.+ source/drain 19.
Referring to FIG. 2C, an inter-layer insulating layer 20 having a predetermined thickness is formed by depositing an insulating material such as a high temperature oxide (HTO) on the substrate. Then, contact holes 22 for connecting the source/drains of the NMOS and PMOS transistors to a wiring layer are formed by selectively removing the inter-layer-insulating layer 20.
Referring to FIG. 2D, a wiring layer 24 is formed by depositing and patterning a conductive material on substrate. The wiring layer 24 electrically contacts the source/drain regions to complete the CMOS structure.
The LDD structure has been used in NMOS transistors to improve reliability. The LDD structure is now often employed in PMOS transistors as well. When device dimensions were larger, it generally was easier to use the LDD structure in the N.sup.- or P.sup.- source/drains because the distance between CMOS devices was large enough. However, as CMOS devices become more highly integrated, and the margin between the N.sup.- source/drain and the P-well, or between the P.sup.- source/drain and the N-well, has generally decreased to under 1 .mu.m, a mere 0.15 .mu.m misalignment of the N-well or P-well can affect operation of the CMOS devices.
Defects in CMOS devices due to the decreased distance between devices will be described below with reference to FIGS. 3, 3A, 4, and 4A. FIG. 3 is a cross-sectional view showing the N.sup.- source/drain of a CMOS transistor electrically connected to the N-well thereof, which generally causes malfunction of the CMOS device. FIG. 3A is an enlarged magnified view of the marked portion shown in FIG. 3.
Referring to FIG. 3, the N-type impurities implanted in the N.sup.- source/drain 12 of the NMOS transistor, or in the N-well 6, are diffused in the lateral direction by subsequent thermal processes. As a result, the N.sup.- source/drain 12 may come into contact with the N-well 6.
In particular, if the impurity concentration in the N.sup.- source/drain is 2.0.times.10.sup.13 ion/cm.sup.2 and the implantation energy is 30 KeV, annealing at 850.degree. C. after forming the N.sup.- source/drain may cause the impurities in the N.sup.- source/drain to diffuse toward the N-well 6 by 0.25 .mu.m. Thus, when the distance 1 between semiconductor devices (see FIG. 1) is 1.0 .mu.m, such diffusion may encompass one fourth of the process margin. Moreover, if the N-well also includes impurities with concentration of 2.0.times.10.sup.13 ion/cm.sup.2 therein, the impurities in the N-well may diffuse toward the N source/drain by 0.25 .mu.m during a subsequent anneal. Thus, when the impurities in the N.sup.- source/drain 12 and the N-well 6 are diffused at the same time, causing the distance therebetween to decrease to 0.5 .mu.m, the N.sup.- source/drain and the N-well may come into contact with each other. When the N.sup.- drain is the output terminal V.sub.OUT and the voltage of the N.sup.+ region providing well bias to the N-well is V.sub.DD, the output voltage V.sub.OUT is equal to V.sub.DD. Thus, improper operation may occur.
FIG. 4 is a cross-sectional view showing misalignment of the P.sup.+ source/drain of a CMOS transistor which can cause malfunction of CMOS devices. FIG. 4A is a enlarged view of the marked portion shown in FIG. 4.
Referring to FIGS. 4 and 4A, when P-type ions are implanted for forming the P.sup.+ source/drain at a high concentration after the implantation of N-type ions at a low concentration into the NMOS and PMOS transistors, P.sup.+ source/drain misalignment may prevent the P-type ions from completely compensating for the implanted N-type ions. Thus, when the wiring layer is formed thereon and voltage is supplied thereto, the remaining N.sup.- source/drain 12 may contact the N-well 6. Thus, the back bias voltage V.sub.BB of the NMOS transistor may be combined with V.sub.DD of the PMOS transistor. A mere 0.1 .mu.m misalignment of the P.sup.+ domain can cause malfunction of a CMOS device and degrade the reliability thereof. Accordingly, there is a need for CMOS integrated circuit structures and fabrication methods which can be highly integrated without undue reliability concerns.